1. Field of the Invention
The present invention relates, in general, to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of the Related Art
In a semiconductor device such as large scale integration (LSI) or the like, a transistor, particularly a MOS transistor, is widely used as a switching device. Generally, the MOS transistor has a structure that includes a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, and source and drain regions which are formed on the semiconductor substrate.
It is known that if the gate length L of the transistor becomes short with the miniaturization of the semiconductor device, the transistor in which short channel effects are not sufficiently restricted is difficult to be turned off, so that threshold voltage Vt becomes lowered. Such dependency of threshold voltage on the gate length is called a Vt-L roll-off characteristic. If the dependency of threshold voltage on the gate length is large approximately at a target gate length, characteristics of a transistor becomes greatly non-uniform because of non-uniformity in fabrication of a gate with the length. Thus, a transistor is needed to be designed such that the dependency of threshold voltage on the gate length becomes reduced.
In order to restrict the short channel effects, it can be taken a measure such as a gate insulating film being made thinner, concentration of impurities in a substrate being made higher, source and drain junctions being made shallow, an adaptation of lightly doped drain (LDD) structure, and the like. Particularly, the LDD structure is suitable to realize a short-channel transistor because it enables not only source and drain junctions contacting a channel to be made shallow without sacrificing electric resistance not much, but also generation of hot electrons to be restricted by raising surface breakdown voltage of drain.
In the LDD structure, offset sidewall spacers formed from a thin insulating film are formed on sidewalls of a gate electrode, and impurities are shallowly and lightly implanted into a semiconductor substrate with the offset sidewall spacers as a mask to form low concentration impurity regions (extension regions). Next, sidewall spacers formed from a thick insulating film are formed on the sides of the offset sidewall spacers, and impurities are deeply and highly implanted into the semiconductor substrate with the sidewall spacers as a mask to form source and drain regions. With the advance of generation, the gate length will be made much shorter, so that only the LDD structure cannot sufficiently restrict the short channel effects. To solve this problem, measures are currently taken, such as forming a halo region in which channel impurities are doped with higher concentration than the ordinal concentration, forming pocket regions in which impurities with the same conductive type as the channel impurities are doped in both sides of a channel in the extension regions, or the like.
A method of forming the conventional LDD structure having the pocket regions will now be described with reference to figures.
FIGS. 8 to 10 are cross-sectional views showing a method of manufacturing a MOS transistor having the conventional LDD structure.
A gate insulating film 2, a gate conductive film 3, and a cap insulating film 4 are formed into the shape of a gate electrode 5 on a p-type semiconductor substrate 1 on which element isolations and wells (not shown) are formed. The gate conductive film 3 may be formed from a polysilicon film, a metal film, or the combination thereof.
Subsequently, a first insulating film, e.g. a silicon oxide film, is formed on the semiconductor substrate 1, and is etched back to form offset sidewall spacers 6b on the sides of the gate electrode 5. Next, n-type impurities are ion-implanted into the semiconductor substrate 1 using the offset sidewall spacers 6b as a mask, thereby forming extension regions 7 (see FIG. 8). Subsequently, p-type impurities are ion-implanted into the semiconductor substrate through slant implantation or the like, thereby forming pocket regions 8 (see FIG. 9).
Next, a second insulating film, e.g. a silicon oxide film, is formed and etched back to form sidewall spacers 9 on the sides of the offset sidewall spacers 6b. Next, n-type impurities are highly doped into the semiconductor substrate 1 using the sidewall spacers 9 as a mask, thereby forming source and drain regions 10 (see FIG. 10).
Here, while the doped impurities are activated by annealing, in this case, the impurities for the extension region are diffused underneath the gate electrode, causing a problem such as an effective gate length Leff being shorten. To inhibit this problem, methods can be taken such as (1) thickening the offset sidewall spacers 6b so as to force the extension regions away from the edges of the gate, (2) raising the concentration of the pocket regions, (3) shallowing the extension regions, and the like.
In case of the method (1), it is effective if the gate pitch is sufficiently large, but with recent tendency to miniaturization of a device, it becomes invalid because the gate pitch becomes narrow, and the thickening may also be impossible because of the restrictions of layout.
In case of the method (2), simply making highly concentrated pocket regions may cause a reverse short channel characteristic, and increases the electric field strength at the end of the drain, causing remarkably hot carrier degradation.
In case of the method (3), if the extension regions are made shallow, parasitic resistance increases, and thus on current of the transistor problematically decreases.
The problem of the method (1) may be solved by the following manner. A thick offset sidewall spacers are formed to separate the extension regions away from the end of the gate, and then the offset sidewall spacers are removed and sidewall spacers to be doped with impurities for source and drain are formed, thereby dealing with the narrowed gate pitch. For example, in order to deal with the narrowed gate pitch, JP A 2006-128540 proposed a method in which lower sidewall spacers are wet-etched to leave a portion thereof on both lower ends of a gate electrode, and then upper sidewall spacers are formed thereon, thereby preventing the thickness of the sidewall spacers from being made excessively thicker.
However, the method of the JP A 2006-128540 has a problem in that the sidewall spacer removal process has to be added. Further, when pocket regions are formed, an ion implantation is carried out after removal of the offset sidewall spacers since effective pocket regions are not formed underneath a gate through the ion implantation into the thickened offset sidewall spacers. Here, in case of using a metal material to form a gate electrode, if the offset sidewall spacers are removed, upon slant implantation for forming the pocket regions, impurity ions also collide with the gate electrode, probably causing metallic contamination due to scattering of the metal material.